PERFORMANCE ANALYSIS OF MULTILAYER INTERCONNECTIONS FOR MEGABIT STATIC RANDOM-ACCESS MEMORY CHIP

The objective of this paper is to analyze interconnection problems in the megabit static random access memory (SRAM) chip. A multilayer inte rconnect capacitance model is developed for the megabit SRAM chip. Int erconnection effects on SRAM device performance parameters, such as pr opagation delay, speed, power consumption, and noise characteristics, are analyzed. A case study of 1-Mb SRAM chip interconnection problems is discussed. A multilayer interconnect approach is proposed for SRAM' s to overcome on-chip interconnection difficulties. Implementing a dou ble-layer interconnect approach, the wire length and chip size were re duced to 69% and 58% respectively. Maximum access time of 30.8 ns with 1 W at 100-degrees-C and wafer yield as high as 10% is achieved. Expe rimental results of multilayer interconnections for the 1-Mb SRAM are provided. The analysis results are found to be very useful for future megabit SRAM's.