A REAL EXPERIENCE ON CONFIGURING A WAFER-SCALE 2-D ARRAY OF MONOBIT PROCESSORS

Authors
BOUBEKEUR A PATRY JL SLIMANEKADI M SAUCIER G TRILHE J
Citation
A. Boubekeur et al., A REAL EXPERIENCE ON CONFIGURING A WAFER-SCALE 2-D ARRAY OF MONOBIT PROCESSORS, IEEE transactions on components, hybrids, and manufacturing technology, 16(7), 1993, pp. 637-645
Citations number
13
Categorie Soggetti
Material Science","Engineering, Eletrical & Electronic
Journal title
IEEE transactions on components, hybrids, and manufacturing technology → ACNP
ISSN journal
01486411
Volume
16
Issue
7
Year of publication
1993
Pages
637 - 645
Database
ISI
SICI code
0148-6411(1993)16:7<637:AREOCA>2.0.ZU;2-1
Abstract
This paper presents hardware and software techniques for configuring a wafer scale 2-D array. A switching network independent of the process ing elements (PE's) has been designed and implemented. Two algorithms find and program an optimized target array in a reversible or irrevers ible manner. This paper is based on a wafer scale design for low-level image processing.