A DYNAMIC RECONFIGURATION SCHEME FOR MEGA BIT STATIC RANDOM-ACCESS MEMORIES

The objective of this paper is to present a novel dynamic reconfigurat ion scheme for mega bit Static Random Access Memories (SRAMs). Most of the conventional reconfiguration methods are implemented using two-wa y switching elements. The proposed scheme is based on on-chip word fai lure detection and reconfiguration to spare word cell using multi-valu ed logic elements. The physical concept of the dynamic reconfiguration scheme and implementation details are discussed. Based on the SRAM dy namic reconfiguration implementation a reliability model is develoed. Dyanamic reconfiguration scheme reliability comparisons with other exi sting methods are presented. The advantages of the proposed dyanamic r econfiguration scheme are highlighted.