AN ANALYTICAL BACK GATE BIAS DEPENDENT THRESHOLD VOLTAGE MODEL FOR SIGE-CHANNEL ULTRATHIN SOI PMOS DEVICES

This paper reports an analytical threshold voltage model for SiGe-chan nel ultrathin SOI PMOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the thresh old voltage. According to the analytical formula, depending on the bac k gate bias, the SiGe-channel SOI PMOS device may have a conduction ch annel at the top or the bottom of the SiGe channel or at the top of th e field oxide.