IMPROVEMENT OF DRY DEVELOPMENT OF PHOTORESIST IN A RIPE SOURCE FOR 0.4 TO 0.35 MU-M TECHNOLOGIES

We present the study of a dry development of silylated resist in a Res onance Inductive Plasma Etcher (RIPE) LUCAS source. An optimised proce ss point has been demonstrated on a device using 0.4 mu m I-line CMOS technology. Top Surface Imaging (T.S.I) is a technique which can push the ultimate resolution of I-line exposure system waiting to a defined DW lithography process. One severe limitation is roughness of the edg e of the pattern. The RIPE source works at low pressure and uses triod e type plasma generation. The combination of low pressure and controll ed bias of the wafer has been demonstrated to be the key point for red ucing the pattern roughness. Compared to Magnetron Reactive Ion Etchin g (MRIE) source, the etch rate uniformity is widely improved. A proces s point has been selected from a parametric study of the RIPE-LUCAS so urce and used for the gate patterning of a 0.4 mu m CMOS device.