SCALING OF POLY-ENCAPSULATED LOCOS FOR 0.35 MU-M CMOS TECHNOLOGY

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 mu m CMOS technology without detrimental effects on gate oxide and sh allow source/drain junction integrity. As-grown bird's beak punchthrou gh is shown to fundamentally limit the scalability of LOCOS-based sche mes for narrow nitride features. A quantitative comparison of bird's b eak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and P ELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We p resent the realization of a 1 mu m active/isolation pitch fully meetin g the geometry and off-leakage requirements of 0.35 mu m CMOS technolo gies (VDS less than or equal to 5 V). This field-implant-free isolatio n module avoids unnecessary process complexity by successfully integra ting scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely widt h-independent down to 0.3 mu m dimensions.