DESIGN AND PERFORMANCE ANALYSIS OF INP-BASED HIGH-SPEED AND HIGH-SENSITIVITY OPTOELECTRONIC INTEGRATED RECEIVERS

Authors
Citation
E. John et Mb. Das, DESIGN AND PERFORMANCE ANALYSIS OF INP-BASED HIGH-SPEED AND HIGH-SENSITIVITY OPTOELECTRONIC INTEGRATED RECEIVERS, I.E.E.E. transactions on electron devices, 41(2), 1994, pp. 162-172
Citations number
29
Categorie Soggetti
Engineering, Eletrical & Electronic","Physics, Applied
ISSN journal
00189383
Volume
41
Issue
2
Year of publication
1994
Pages
162 - 172
Database
ISI
SICI code
0018-9383(1994)41:2<162:DAPAOI>2.0.ZU;2-I
Abstract
A novel transimpedance optoelectronic receiver amplifier suitable for monolithic integration is proposed and analyzed by exploiting state-of -the-art high-speed MSM photodiodes and HBT's based on lattice-matched InGaAs/InAlAs heterostructures on InP substrates. The projected perfo rmance characteristics of this amplifier indicate a high transimpedanc e (almost-equal-to 3.6 kOMEGA), a large bandwidth (17 GHz), and an exc ellent optical detection sensitivity (-26.8 dBm) at 17 Gb/s for the st andard bit-error-rate of 10(-9). The latter corresponds to an input no ise spectral density, square-root i(in)2/B, of 2.29 pA/square-root Hz for the full bandwidth. The bandwidth of the amplifier can be increase d to 30 GHz for a reduced transimpedance (0.82 kOMEGA) and a lower det ection sensitivity, i.e., -21 dBm at 30 Gb/s. The amplifier also achie ves a detected optical-to-electrical power gain of 21.5 dBm into a 50 OMEGA load termination. The design utilizes small emitter-area HBT's f or the input cascoded-pair stage, followed by a two-step emitter-follo wer involving one small and one large emitter-area HBT's. The design s trategy of using small emitter-area HBT's is matched by a low-capacita nce novel series/parallel connected MSM photodiode. This combined appr oach has yielded this amplifier's combined high performance characteri stics which exceed either achieved or projected performances of any re ceiver amplifier reported to-date. The paper also discusses the issues concerning IC implementation of the receiver, including the means of realizing a high-value feedback resistor.