F. Assaderaghi et al., DYNAMIC THRESHOLD-VOLTAGE MOSFET (DTMOS) FOR ULTRA-LOW VOLTAGE VLSI, I.E.E.E. transactions on electron devices, 44(3), 1997, pp. 414-422
In this paper, we propose a novel operation of a MOSFET that is suitab
le for ultra-low voltage (0.6 V and below) VLSI circuits, Experimental
demonstration was carried out in a Silicon-On-Insulator (SOI) technol
ogy, In this device, the threshold voltage of the device is a function
of its gate voltage, i.e., as the gate voltage increases the threshol
d voltage (V-t) drops resulting in a much higher current drive than st
andard MOSFET for low-power supply voltages. On the other hand, V-t is
high at V-gs = 0, therefore the leakage current is low. We provide ex
tensive experimental results and two-dimensional (2-D) device and mixe
d-mode simulations to analyze this device and compare its performance
with a standard MOSFET. These results verify excellent inverter de cha
racteristics down to V-dd = 0.2 V, and good ring oscillator performanc
e down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).