DESIGN OF IGBTS FOR LATCH-UP FREE OPERATION

An N-type buffer region is introduced into the N+ source of the IGBT t o make it latch-up free. This is done by controlling the resistances o f the buffer N region and the P base. A latch-up free condition based on these resistances is presented. 2D numerical simulation is used to demonstrate the concept and the results show that the device can be ma de to be latch-up free by decreasing the doping concentration of the N -buffer or increasing the doping in the P base in accordance with this condition. Further, a control gate is introduced into the buffer laye r to control its resistance and the simulation results show that latch -up can also be eliminated by applying a sufficiently negative voltage on this gate. Lastly, the effect of the MOS gating level on the latch -up for IGBT is given, and the results are discussed qualitatively.