HOT-CARRIER-RELIABILITY DESIGN RULES FOR TRANSLATING DEVICE DEGRADATION TO CMOS DIGITAL CIRCUIT DEGRADATION

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulat or BERT can predict CMOS digital circuit speed degradation from transi stor DC stress data. Initial fast degradation is noted and attributed to the ''zero crossing'' effect caused by PMOSFET current enhancement. Saturation drain current, measured at V(gs) = V(ds) = Vdd/2, is a bet ter monitor for CMOS circuit hot-carrier reliability. We present gener alized hot-carrier-reliability design rules, lifetime and speed factor s, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estima te the overall product hot-carrier reliability. The NMOSFET and PMOSFE T lifetime factors are found to obey 4/ft(rise) and 10/ft(fall), respe ctively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 12 0 and 300, respectively.