ON THE EFFECT OF FLOORPLANNING ON THE YIELD OF LARGE-AREA INTEGRATED-CIRCUITS

Until recently, VLSI designers rarely considered yield issues when sel ecting a floorplan for a newly designed chip, This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yi eld, We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips, We conclude tha t the floorplan of a chip can affect its projected yield in a nonnegli gible way, for chips with or without fault-tolerance.