SYNTHESIS OF PIPELINED DSP ACCELERATORS WITH DYNAMIC SCHEDULING

To construct complete systems on silicon, application specific DSP acc elerators are needed to speed up the execution of high throughput DSP algorithms, In this paper, a methodology is presented to synthesize hi gh throughput DSP functions into accelerator processors containing a d atapath of highly pipelined, bit-parallel hardware units. Emphasis wil l be put on the definition of a controller architecture that allows ef ficient run-time schedules of these DSP algorithms on such highly pipe lined data paths, The methodology will be illustrated by means of an i mage encoding filter bank.