POWER ANALYSIS AND MINIMIZATION TECHNIQUES FOR EMBEDDED DSP SOFTWARE

Power is becoming a critical constraint for designing embedded applica tions. Current power analysis techniques based on circuit-level or arc hitectural-level simulation are either impractical or inaccurate to es timate the power cost for a given piece of application software. In th is paper, an instruction-level power analysis model is developed for a n embedded digital signal processor (DSP) based on physical current me asurements. Significant points of difference have been observed betwee n the software power model for this custom DSP processor and the power models that have been developed earlier for some general-purpose comm ercial microprocessors [1], [2]. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special ar chitectural features that allow dual-memory accesses and packing of in structions into pairs. The energy reduction possible through the use o f these features is studied, The on-chip Booth multiplier on the proce ssor is a major source of energy consumption for DSP programs. A micro architectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level pow er model is proposed. Several example programs are provided to illustr ate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that t he energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In add ition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.