SCALING THE MOS-TRANSISTOR BELOW 0.1 MU-M - METHODOLOGY, DEVICE STRUCTURES, AND TECHNOLOGY REQUIREMENTS

This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 mum. Limits imposed on the scalability o f oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibil ity of achieving sub-0.1 mum MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different dev ice structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valua ble starting point for the understanding of technological requirements for future ULSI.