A FULLY COMPLEMENTARY BICMOS TECHNOLOGY FOR 10 V MIXED-SIGNAL CIRCUITAPPLICATIONS

A 10 V fully complementary BiCMOS technology, HBC-10, has been develop ed for high speed, low noise and high precision mixed signal system in tegration applications. In this technology, two varieties of CMOS tran sistors have been implemented for 10 V analog and 5 V digital applicat ions. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS tr ansistors with a lightly doped drain extension added to the NMOS struc ture to achieve device lifetime in excess of 10 years. A gate oxide th ickness of 18 nm is used for 5 V CMOS logic circuits. These transistor s are specially architected so that they may also serve as analog tran sistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed bv use of a double diffused drain structure. The active devices are isolated bv a fully recessed 1.5 mum oxide grown under hig h pressure conditions. Use of high pressure steam, plus combining diff usion operations where possible, results in a low overall thermal budg et. This allows the up-diffusion of buried layers to be minimized so t hat a thin, 1.6 mum epitaxial silicon layer is sufficient to support 1 0 V bipolar transistors. The resultant vertical PNP and NPN transistor s are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more tha n 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxid e-polysilicon capacitor and trimmable thin film resistor are integrate d into this process. This wide variety of passive and active component s is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operati ons is 23, which includes double layer metallization.