Under cryogenic operation, a low V(th) realizes a high speed performan
ce at a greatly reduced power-supply voltage, which is the most attrac
tive feature of Cryo-CMOS. It is very important in sub-0.25 mum Cryo-C
MOS devices to reconcile the miniaturization and the low V(th). Double
implanted MOSFET's technology was employed to achieve the low V(th) w
hile maintaining the short channel effects immunity. We have investiga
ted both the DC characteristics and the speed performance of 0.25 mum
gate length CMOS devices for cryogenic operation. The measured transco
nductances in the saturation region were 600 mS/mm for 0.2 mum gate le
ngth n-MOSFET's and 310 mS/mm for 0.25 mum gate length p-MOSFET's at 8
0 K. The propagation delay time in the fastest CMOS ring oscillator wa
s 22.8 ps at V(dd) = 1 V at 80 K. The high speed performance at extrem
ely low power-supply voltages has been experimentally demonstrated. Th
e speed analysis suggests that the sub-10 ps switching of Cryo-CMOS de
vices will be realized by reducing the parasitic capacitances and thro
ugh further miniaturization down to 0.1 mum gate length or below.