PERFORMANCE AND RELIABILITY EVALUATION OF HIGH DIELECTRIC LDD SPACER ON DEEP-SUBMICROMETER LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliabili ty and performance improvement on the scaled LDD MOSFET's. However, th e sidewall polyoxide and spacer bottom oxide required for process reli ability issue will adversely limit the DC performance improvement gain ed by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconducta nce, G(M) and total gate capacitance, C(GG). For deep-submicron MOSFET 's, the dominance of gate to source/drain overlap capacitance in C(GG) has significant impact on the AC performance. The increase of C(GG) d ue to the enhanced fringe field from high dielectric LDD spacer signif icantly dominates over the increase of transconductance, and then dete riorates the AC performance. As the reliability issue is concerned, th e key doping profile, N- source/drain lateral diffusion profile was ob tained from the two dimensional process simulator SUPREM-IV correspond ing to wide range of LDD N- doses. The optimized V- dose designed for hot carrier reliability issue (under V(GS) - V(T) = 0.5V(DS) operation ) is located around 2 x 10(13) cm-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. Howeve r, the improvement achieved by using HLDD instead of OLDD devices is t hen turned out to be insignificant under this optimized N- dose condit ion.