GAP FILLING WITH PVD PROCESSES FOR COPPER METALLIZED INTEGRATED-CIRCUITS

The paper presents the results of two PVD techniques used for trench a nd via filling in copper-based metallization systems. The structure si ze is scaled down to 0.5 mu m and the aspect ratio (ratio of depth to width) is coming up to about 2.5. The patterning of the copper lines i s performed by CMP (damascene technique). The first de magnetron sputt ering is optimized for trench filling with aspect ratios up to 1 by us ing variation of the distance between the substrate and the sputter ta rget. It is shown that this variation is more effective for getting be tter filling results in comparison with variation of the deposition pa rameters like de power, substrate temperature and substrate rf bias. B esides alternative investigated filling techniques like copper reflow, copper self-sputtering or ICP/ECR-based ionised sputtering the second high current pulsed are deposition is performed to reach void-free fi lled vias and trenches with aspect ratios of 2. The typical problem wi th droplets is minimized. The first results show that the performance of this PVD technique is comparable with those of the above-mentioned filling methods and with copper CVD too. Additionally, it seems possib le to use the deposition process in such a way that a Ta diffusion bar rier can be deposited either conformally or without a noticeable layer growth on the top of the structure.