MATERIALS AND PROCESSING FOR 0.25 MU-M MULTILEVEL INTERCONNECT

A new generation of interconnect schemes is required for high performa nce ULSI. This involves developing process modules aimed at reducing R C delay and power consumption, as well as developing new equipment tec hnology to support these processes. In the materials area, the most si gnificant challenge is to define a workable and reliable combination o f high conductivity metals (Al(Cu), Cu) with a low dielectric constant insulator (starting with fluorinated silicon oxide). As far as proces sing is concerned, the key technological issues that we will address i n this paper are (i) etching dielectrics and metals with high aspect r atio (4:1 for contact/via and greater than 1.5:1 for lines/trenches) a nd (ii) filling these aggressive topologies using dielectric films wit h high gap-filling capabilities and conformal/planarizing CVD and PVD metal deposition. Besides the option of using SiOF dielectric and oxid e CMP, four process modules of interconnects can be highlighted: (1) g ap-fill oxide/W interconnect and/or via plug/metal etch; (2) gap-fill oxide/via fill and planarized Al/metal etch; (3) metal plug/metal dama scene; and (4) Cu dual damascene. Since time-to-market will still be v ery critical for fabrication at 0.25 mu m technology, typically for 20 0 mm and 300 mm wafers, the challenge is clearly to achieve successful vertical and horizontal integration of these modules. As a result, mo re than ever, suppliers and chip manufacturers have to work very close ly at early stages of technology development. Examples of joint develo pment programs leading to new breakthroughs in technology and reactor design will be discussed.