INTERCONNECT PARASITICS EVALUATION AND OPTIMIZATION

Several process-related interconnect parasitic effects are investigate d for standard CMOS 0.35 and 0.25 mu m, with the help of PATRICE, a 2D electromagnetic field solver developed by the Grenoble university lab oratory LEMO. The effects of the Ti/TiN barrier layers and of a slight ly trapezoidal cross-section on line resistance and capacitance are st udied. The capacitance increase linked to an underlying nitride layer is also evaluated, as well as the influence of the passivation process on capacitances. A set of four interconnection schemes is proposed to reduce parasitic ground and coupling capacitances and thus enhance te chnology performance. These strategies consist of: increasing the inte rmetal dielectric (IMD) thicknesses, using SiOF instead of SiO2, embed ding the lines in a low-permittivity dielectric, and switching to copp er metallizations with constant line resistance. The effectiveness of these schemes is checked for the capacitances of simple 2D structures and for delay, crosstalk and consumption in typical circuit routings.