CELLULAR-AUTOMATA AS A BIST STRUCTURE FOR TESTING CMOS CIRCUITS

Two-patterns are required to test single stuck-open faults in CMOS cir cuits, while detection of multiple stuck-open faults requires the appl ication of three-patterns. The regular, modular and cascadable structu re of cellular automata (CA) has been proposed as a built-in self-test (BIST) structure for on-chip generation of two-pattern and three-patt ern test vectors. An analytical tool has been developed to characteris e the properties of CA as a test pattern generator for CMOS circuits. The conditions to generate exhaustive two-patterns and three-patterns of n-bits have been investigated. Based on matrix algebraic analysis, it is shown that a specific class of CA satisfying this condition can be employed as a BIST structure for testing CMOS circuits. A lower bou nd on CA size has been analytically established. Criteria for the sele ction of the most desirable CA structure have also been presented alon g with the experimental results for a set of real-life circuits.