EFFICIENT MODELING AND SYNTHESIS PROCEDURE OF ASYNCHRONOUS SEQUENTIALLOGIC ELEMENTS

A model and procedure are developed for synthesising asynchronous sequ ential logic elements (ASLEs). This model represents the functional be haviour with a more compact form, and the procedure can synthesise the m more efficiently than the traditional one. With the delineation of i nputs as mode inputs, level inputs and edge inputs from the design spe cification, a set of equations can be generated which describes the lo gic module's functional behaviour. The calculated states from these eq uations have bipartite adjacency relationships, which can easily be ma pped onto an n-cube to obtain race-free state assignments. This proced ure can also be applied for the synthesis of an asynchronous sequentia l logic circuit (ASLC) which has many data inputs and a small number o f control inputs.