A LOW-CAPACITANCE BIPOLAR BICMOS ISOLATION TECHNOLOGY .1. CONCEPT, FABRICATION PROCESS, AND CHARACTERIZATION

A device isolation structure for low-parasitic bipolar transistor inte gration is presented. The concept involves two selective epitaxial gro wth steps (SEG) and two polishing cycles which replace the collector-e pitaxy and the deep/shallow trench formation in conventional device is olation. With an optimum device layout, the collector-substrate capaci tance is reduced to congruent-to 30%, the collector-base capacitance t o congruent-to 70%, and the extrinsic base contact resistance to <50% compared to trench isolation. The combination of SEG and polishing mak es it possible to form SOI regions with locally different SOI thicknes ses on the same wafer, so that fully depleted CMOS and vertical bipola r transistors can be combined in a SOI-BiCMOS technology.