FSMTEST - SYNTHESIS FOR TESTABILITY AND TEST-GENERATION OF PLA-BASED FSM

A new hardware scheme for easily testable PLA-based finite state machi nes is proposed. With this scheme, all combinationally irredundant cro sspoint faults in the PLA logic implementation are testable. Moreover, test generation is easily accomplished because short systematic initi alisation sequences exist for each internal state in the machine and u nit length distinguishing sequences, which hold under the faulty condi tion existing for every true-faulty state pair. This paper presents an outline of the proposed scheme, which consists basically in the addit ion of some state transitions and their output to the state transition graph (STG) of the machine. A test generation procedure is described which requires neither fault simulation, nor manipulation of the machi ne's STG.