EFFECTS OF HOT-CARRIER-INDUCED INTERFACE STATE GENERATION IN SUBMICRON LDD MOSFETS

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variatio n of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of con duction charge due to interface traps are considered. A 0.6 mum LDD MO SFET was fabricated. The drain current degradation and the substrate c urrent variation after a stress were characterized to compare the simu lation. A reduction of the substrate current at V(g) congruent-to 0.5 V(d) in a stressed device was observed from both the measurement and t he simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated inter face states.