INTEGRATED PROCESSING OF STACKED-GATE HETEROSTRUCTURES - PLASMA-ASSISTED LOW-TEMPERATURE PROCESSING COMBINED WITH RAPID THERMAL HIGH-TEMPERATURE PROCESSING

We discuss a novel approach to the formation of deposited stacked-gate structures that combines several different processing steps into a si ngle chamber with multi-function oxidation, passivation and deposition capabilities. To form a Si-based stacked gate structures the followin g in-situ steps can be performed i) a final cleaning/passivation of th e Si surface, ii) formation of the SiO2/Si interface, iii) deposition of a single, or multi-layer dielectric, e.g., SiO2, or an oxide/nitrid e/oxide (ONO) structure, and iv) deposition of a polysilicon gate elec trode. We discuss the fabrication and performance of test device struc tures that combine remote plasma and rapid thermal processing steps, b ut omit the polysilicon deposition, and use an Al gate electrode inste ad. These structures are use to demonstrate the effectiveness of diffe rent interface formation processes.