GENERATION OF INHERENTLY PERIODICAL TEST PATTERNS FOR THE E-BEAM TESTOF SCAN-BASED DESIGNS

Due to reliability and economic aspects, fault diagnosis comes up to b e an essential aid for manufacturing highly integrated circuits. Elect ron beam testing is a common technique for fault diagnosis purposes. I t allows the observation of voltages at internal circuit nodes. If mea surements with high voltage and time resolutions are requested and lar ge circuits have to be investigated, long measurement times have to be accepted or measurements are even impossible. Up to now no software t ools have been presented which support high resolution measurements wi th the electron beam test. Considering scan-based circuit designs, thi s paper describes a new concept and the generation of inherently perio dical test patterns leading to a reduction of electron beam test measu rement times. Our approach meets hardware difficulties with applying s tate-of-the-art test pattern generation. Computational results show th at a drastic reduction of measurement times can be obtained by applyin g inherently periodical test patterns. Reduction factors for ISCAS ben chmark circuits range between 4 and 255. Therefore, high resolution me asurements can be carried out in reasonable times.