The direct binary hypercube interconnection network has been widely us
ed in the design of parallel computer systems, because it has low diam
eter, and can effectively emulate commonly used structures such as bin
ary trees, rings, and meshes. However, the hypercube has the disadvant
age of high VLSI complexity due to the increase in the number of commu
nication ports and channels per PE (processing element) with an increa
se in the dimension of the hypercube. This complexity is a major drawb
ack of the hypercube because it limits its potential for scalability.
Ziavras has introduced the reduced hypercube (RH) interconnection netw
ork. The RH reduces VLSI complexity without compromising performance.
The RH is obtained from a regular hypercube by a uniform reduction in
the number of edges for each hypercube node. The main objective of thi
s paper is tb demonstrate the feasibility of the RH in implementing ma
terial identification algorithms using X-ray fluorescence. Relevant al
gorithms are developed for the PRAM and the hypercube also, for compar
ative analysis. The algorithms rely heavily on the binary tree emulati
on capabilities of these systems. The results indicate that the RH is
capable of providing hypercube-like performance at a significantly red
uced complexity/cost. Copyright (C) 1996 Elsevier Science Ltd