0.3-MU-M MIXED ANALOG-DIGITAL CMOS TECHNOLOGY FOR LOW-VOLTAGE OPERATION

A 0.3-mum mixed analog/digital CMOS technology for low-voltage operati on has been demonstrated, including a new MOSFET structure with latera lly doped buried layer (LDB) and a double-polysilicon capacitor with l ow voltage coefficient. The LDB-structure MOSFET provides constant thr eshold voltage which is independent of channel length, high current dr ivability 10% over that of a conventional structure, and low junction capacitance which is less than 1/2 that of the conventional structure. The double-polysilicon capacitor achieves a voltage coefficient of 1/ 10 that of a conventional capacitor by introducing arsenic ion implant ation to the top polysilicon plate and a Si3N4 capacitor-insulator, de spite the insulator thickness being scaled down to oxide-equivalent 20 nm.