SELF-ALIGNED SILICON FIELD-EMISSION CATHODE ARRAYS FORMED BY SELECTIVE, LATERAL THERMAL-OXIDATION OF SILICON

This article reports on the fabrication of single crystal silicon, fie ld emission tip arrays. The tips are formed by exposing a ''capped'' s ilicon pedestal to a lateral high temperature thermal oxidation. Tips formed using this process have uniform height and profile, and have sm all radii of curvature-typically less than 20 nm. We have fabricated t ip arrays with up to 2500 elements and with the tip-to-tip spacing ran ging from 1.0 to 5.0 mum. The thermal SiO2 has a nominal thickness of 600 nm and serves as insulation between the extraction grid and the su bstrate. The extraction grid is a self-aligned, sputter deposited Ti0. 1W0.9 film. Extraction grid apertures range from 900 nm to 1.7 mum. Th e process sequence is flexible allowing the fabrication of tips with d ifferent heights. The vertical position of the tip apex with respect t o the extraction grid aperture, therefore, is a controllable parameter . The preliminary emission measurements are presented here for arrays containing 400 elements. All testing is done in ultrahigh vacuum (typi cally less than 5.0 X 10(-10) Torr). The areas of the arrays fabricate d range from 40 mum X 40 mum to 100 mum X 100 mum. The tip heights ran ge from 1.0 to 1.4 mum above the substrate silicon. The maximum curren t produced from a 400 element array is only 0.45 muA at 140 V(dc). The low array current indicates that only a small number of tips are acti ve at a given voltage.