G. Czech et al., REDUCTION OF LINEWIDTH VARIATION FOR THE GATE CONDUCTOR LEVEL BY LITHOGRAPHY BASED ON A NEW ANTIREFLECTIVE LAYER, Microelectronic engineering, 21(1-4), 1993, pp. 51-56
An antireflective bilayer consisting of a-SiN on top of a-Si has been
developed in particular for the application over gate level topography
with a TEOS/polySi substrate stack furnishing high substrate reflecti
vity, especially in case of i-line exposure. The increase in complexit
y of the optimized overall-process seems acceptable in view of the dis
tinctly reduced CD variations obtained with 16M g- and i-line lots whe
n compared to the standard technique using dyed resist.