CIRCUIT-DESIGN GUIDELINES FOR N-CHANNEL MOSFET HOT-CARRIER ROBUSTNESS

We present a methodology for developing CMOS circuit design guidelines that ensure adequate ac hot carrier lifetimes for n-MOSFET's and appl y it to a 3.3-V, 0.75-mum technology. We implement our ac hot-carrier degradation model in a lifetime simulator. After determining worst cas e voltage conditions during operation, we simulate typical circuit con figurations. Speed binning considerations indicate that the hot-carrie r lifetime simulations be performed for the slowest device in the fast est bin. We find that capacitive coupling is a major source of voltage excursions that can lead to low hot-carrier lifetimes. While interfac e-state generation dominates the degradation of most n-MOSFET's, these transistors also have large lifetimes. Damage due to hole injection a t low gate voltages must be taken into account in order to identify de vices with unacceptably low lifetimes. Based upon simulation results, we formulate a coherent set of device level and circuit level guidelin es for hot carrier robust design. At the device level, the guidelines restrict the duty cycles in specific bias domains, and place limits up on the maximum voltages applicable. At the circuit level, these restri ctions are reflected in rules that limit the total nodal capacitance p er unit W/L of the driving device to 0.06 pF per W/L, that require the ratio of coupling capacitance to total nodal capacitance be less than 0.2 and constrain the magnitude of other noise sources. These restric tions are compatible with standard design practices and design tools f or ensuring circuit performance and noise immunity.