HIGH-SPEED GAAS MULTIPLIERS FABRICATED WITH A HIGH-YIELD 0.4-MU-M PROCESS

For high-speed LSI digital applications, we have developed a 0.4-mum G aAs IC fabrication process which demonstrates excellent yields for dir ect-coupled FET logic circuits of up to 5000 gates. The refractory sel f-aligned gate process uses 1-mum stepper lithography. An n+/n'/buried -p structure results in superior threshold voltage uniformity for a 0. 4-mum gate length, with sigmaV(T) as low as 8 mV over 3-in wafers. Sim ple parallel array multipliers were used for process validation. Die-s ort yields for a 16 x 16-b multiplier are typically better than 55%, a nd as high as 88%. A 5000-gate 20 x 20-b multiplier shows yield as hig h as 61%, and a Poisson yield model predicts a die-sort yield of 30% f or a 10 000-gate circuit. Multiplication times of 3.6 ns for the 16 x 16-b and 4.5 ns for the 20 x 20-b multiplier have been measured. The c orresponding loaded gate delay of 46 ps/gate and power-delay product o f 40 fJ are unequaled among values reported for LSI circuits at room t emperature.