PLASMA ETCH PROCESSING OF ADVANCED FERROELECTRIC DEVICES

Ferroelectric structures are being used in SRAM devices and are migrat ing to DRAM devices. A DRAM cell size can be dramatically reduced by e mploying ferroelectric structures in place of the current silicon oxid e capacitor structures. A 5 mu(2) DRAM cell capacitor can be reduced i n size by a factor of 20 using a ferroelectric structure. The current technology used to etch ferroelectric device layers has at least two m ajor shortcomings. The first etch issue is the sloped profiles (i.e. 4 0 degrees) which are a result of the high ion energies used to etch th e relatively non volatile materials (Platinum and PZT). The second etc h issue is severe sidewall redeposition when vertical profiles are obt ained by using ion mills etc. The etch products that are redeposited o n the sidewalls become very difficult or impossible to remove in a man ufacturing environment. Profiles of > 75 degrees without heavy redepos ition will be required in order for 0.5 mu DRAMs to be produced using ferroelectric technology. A series of designed experiments were develo ped to understand the dependent variables impact on reducing residues and increasing the etched feature's profile angle. Response surfaces w ere developed for resist selectivity, profile angle, and etch rate ver sus changes in KHz power, cathode temperature, reactant gas flow and a dditive gas flow in an HRe- (High Density Reflected Electron) etch sys tem. The process results (optical emission and SEM analysis) were stat istically evaluated and process trends developed. The resulting respon se surface graphs combined with SEM micrographs demonstrate trends in profile control and etch rate. The process trends are reviewed which r esult in > 75 degrees residue-free etching of ferroelectric devices.