COMBINING TECHNOLOGY MAPPING WITH LAYOUT

Due to the significant contribution of interconnect to the area and sp eed of today's circuits and the technological trend toward smaller and faster gates which will make the effects of interconnect even more su bstantial, interconnect optimization must be performed during all phas es of the design. The premise of this paper is that by increasing the interaction between logic synthesis and physical design, circuits with smaller area and interconnection length, and improved performance and routability can be obtained compared to when the two processes are do ne separately. In particular, this paper describes an integrated appro ach to technology mapping and physical design which finds solutions in both domains of design representation simultaneously and interactivel y. The two processes are performed in lockstep: technology mapping tak es advantage of detailed information about the interconnect delays and the layout cost of various optimization alternatives; placement itsel f is guided by the evolving logic structure and accurate path-based de lay traces. Using these techniques, circuits with smaller area and hig her performance have been synthesized.