STATISTICAL MODULE LEVEL AREA AND DELAY ESTIMATION

The increasing complexity of VLSI design process has led to an increas ing use of layout synthesis systems. For many components of a high-lev el synthesis system such as module generators and module generator dev elopment environments, an accurate model of area and delay for the lay outs generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of func tion modules. This model is surprisingly accurate for a standard cell based layout synthesis system-VPNR. The area of adder and shifter modu les can be modeled to with in 5% accuracy while the error in delay mod el is bounded by 48. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coefficient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the t emplate.