MODULE SELECTION IN MICROARCHITECTURAL SYNTHESIS FOR MULTIPLE CRITICAL CONSTRAINT SATISFACTION

Accurate design descriptions during synthesis allow efficient use of r esources. The appropriate use of distinct implementations of RTL opera tors helps generate optimal VLSI designs. The system presented here ut ilizes libraries composed of multiple modules with identical functiona lity, but distinct performance and area characteristics. Such librarie s allow the generation of an accurate estimate of the area and delay o f the final design during synthesis. Full use of the module selection capability is possible by allowing the user to specify a total area li mit rather than a detailed allocation. Consequently, tradeoffs between different allocations can be fully explored. Scheduling, module selec tion, and allocation are performed simultaneously to achieve optimal u se of area and delay, and to facilitate the incorporation of lower lev el design considerations into behavioral synthesis. Synthesis decision s are made in a time-constrained and area-constrained fashion, by usin g both constraints to identify and avoid infeasible design possibiliti es. Module selection, scheduling, and allocation for pipelined designs is also implemented. Experimental results show that the use of module selection and rime-and-area-constrained synthesis results in an area/ delay design curve which is superior to the results of traditional sys tems.