M. Eisele et al., THE IMPACT OF INTRA-DIE DEVICE PARAMETER VARIATIONS ON PATH DELAYS AND ON THE DESIGN FOR YIELD OF LOW-VOLTAGE DIGITAL CIRCUITS, IEEE transactions on very large scale integration (VLSI) systems, 5(4), 1997, pp. 360-368
The yield of low voltage digital circuits is found to be sensitive to
local gate delay variations due to uncorrelated intra-die parameter de
viations, Caused by statistical deviations of the doping concentration
they lead to more pronounced delay variations for minimum transistor
sizes, Their influence on path delays in digital circuits is verified
using a carry select adder test circuit fabricated in 0.5 and 0.35 mu
m complementary metal-oxide-semiconductor (CMOS) technologies with two
different threshold voltages, The increase of the path delay variatio
ns for smaller device dimensions and reduced supply voltages as well a
s the dependence on the path length is shown. It is found that circuit
s with a large number of critical paths and with a low logic depth are
most sensitive to uncorrelated gate delay variations, Scenarios for f
uture technologies show the increased impact of uncorrelated delay var
iations on digital design, A reduction of the maximal clock frequency
of 10% is found for e.g. highly pipelined systems realized in a 0.18-m
u m CMOS technology.