A 0.5 V SINGLE POWER-SUPPLY OPERATED HIGH-SPEED BOOSTED AND OFFSET-GROUNDED DATA-STORAGE (BOGS) SRAM CELL ARCHITECTURE

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses a boosted and offset-grounded data storage (B OGS) scheme, The key target of BOGS is to minimize the charge amount s upplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V-O = V-GS - V-T) up to 0. 8 V necessary to achieve 100 MHz operation even at 0.5 V single power supply, Thus, the key low-pow er strategy of BOGS is ''putting the rig ht (higher efficiency) boosted power-supply from charge pump circuit i nto the right position (less power consumed transistor) in a SRAM cell .'' This paper is focused on why BOGS can realize a greater savings of the charge amount supplied from the boosted power-line and can reduce the power dissipation to less than or equal to 1/30.4 and less than o r equal to 1/3.9 compared to the previously reported negative source-l ine drive (NSD) scheme [1] and negative word-line drive (NWD) scheme [ 2], respectively, while achieving a 0.5 V/100 MHz operation.