EXPLORING THE DESIGN SPACE OF MIXED SWING QUADRAIL FOR LOW-POWER DIGITAL CIRCUITS

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of d igital circuits in standard submicron complementary metal-oxide-semico nductor (CMOS) fabrication processes, Employing mixed voltage swings e xpands the degrees of freedom available in the power-delay optimizatio n space of static CMOS circuits. In order to study this design space a nd evaluate the power-delay tradeoffs, analytical posynomial formulati ons for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy, Effic ient voltage scaling and transistor sizing techniques based on our ana lytical formulations are proposed for optimizing energy/operation subj ect to target delay constraints; up to 2.2x improvement in energy/oper ation is demonstrated for an ISCAS'85 benchmark circuit using these te chniques, Experimental results from HSPICE simulations and measurement s from an And-Or-Invert (AOI222) test chip fabricated in the Hewlett-P ackard 0.5 mu m process are presented to demonstrate up to 2.92x energ y/operation savings for optimized mixed swing circuits compared to sta tic CMOS.