GATE-LEVEL POWER AND CURRENT SIMULATION OF CMOS INTEGRATED-CIRCUITS

In this paper, we present a new gate-level approach to power and curre nt simulation, We propose a symbolic model of complementary metal-oxid e-semiconductor (CMOS) gates to capture the dependence of power consum ption and current hows on input patterns and fan-in/fan-out conditions . Library elements are characterized once for all and their models are used during event-driven logic simulation to provide power informatio n and construct time-domain current waveforms, We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while ke eping performance comparable with traditional gate-level simulation wi th unit delay. We use VERILOG-XL as simulation engine to grant compati bility with design tools based on Verilog HDL, A Web-based user interf ace allows our simulator (PPP) to be accessed through the Internet usi ng a standard web browser.