BACK-GATED CMOS ON SOIAS FOR DYNAMIC THRESHOLD VOLTAGE CONTROL

The simultaneous reduction of power supply and threshold voltages for low-power design without suffering performance losses will eventually reach the limit of diminishing returns as static leakage power dissipa tion becomes a significant portion of the total power consumption, Thi s is especially acute in systems that are idling most of the time. In order to meet the opposing requirements of high performance at reduced power supply voltage and low-static leakage power during idle periods , a dynamic threshold voltage control scheme is proposed. A novel Sili con-On-Insulator (SOI)-based technology called Silicon-On-Insulator-wi th-Active-Substrate (SOIAS) was developed whereby a bark-gate is used to control the threshold voltage of the frontgate; this concept was de monstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators. For a 250 mV switch in threshold voltage , a reduction of 3-4 decades in subthreshold leakage current was measu red.