A comprehensive study of the device layout effects on thermal resistan
ce in thermally-shunted heterojunction bipolar transistors (HBTs) was
completed. The thermal resistance scales linearly with emitter dot dia
meter for single element HBTs. For multiple emitter element devices, t
he thermal resistance scales with area. HBTs with dot geometrics have
lower thermal impedance than bar HBTs with equivalent emitter area. Th
e thermal resistance of a 200 mu m(2) emitter area device was reduced
from 266 degrees C/W to 146 degrees C/W by increasing the shunt thickn
ess from 3 mu m to 20 mu m and placing a thermal shunt landing between
the fingers. Also, power-added efficiencies at 10 GHz were improved f
rom 30% to 68% by this thermal resistance reduction. Published by Else
vier Science Ltd.