ISSUES FOR MULTILEVEL METALLIZATION IN HIGH-DENSITY CIRCUITS (INVITEDLECTURE)

Authors
JOSWIG H BARTH HJ ELBEL N PENKA S
Citation
H. Joswig et al., ISSUES FOR MULTILEVEL METALLIZATION IN HIGH-DENSITY CIRCUITS (INVITEDLECTURE), Microelectronic engineering, 37-8(1-4), 1997, pp. 15-27
Citations number
16
Journal title
Microelectronic engineering → ACNP
ISSN journal
01679317
Volume
37-8
Issue
1-4
Year of publication
1997
Pages
15 - 27
Database
ISI
SICI code
0167-9317(1997)37-8:1-4<15:IFMMIH>2.0.ZU;2-W
Abstract
As lateral dimensions shrink in high density circuits, metal and diele ctric film thickness are not scaled down at the same pace. This leads to several technological challenges in multilevel interconnects. This article focuses on some of them: contact and via fill processes, optio ns in intermetal dielectrics, and planarization issues. Also, a short outlook on innovative interconnect architecture and novel materials is given.