Selective chemical vapor deposition (CVD) of TiSi2 has been obtained f
rom TiCl4/DCS/H-2 chemistry using an industrial integrated cluster rea
ctor. First, some fundamental aspects were studied in order to better
understand the process. Prior to deposition, an incubation time exists
which increases with decreasing deposition temperature. For temperatu
res between 650 and 780 degrees C, the growth rate is limited by the T
iCl4 flow. This CVD technique was then used on device wafers and we ob
tained low sheet resistances of down to 0.2 mu m in poly linewidth and
0.12 mu m in active area width. Leakage currents on diode structures
are shown to be essentially dependent on residual implantation defects
, and thus, on implantation conditions. To conclude, CVD TiSi2 has bee
n validated on a microprocessor circuit fabricated in a 0.35 mu m CMOS
process and the yield obtained is comparable to that obtained using t
he standard salicide technique with fewer technological steps.