DEGRADATION MEASUREMENTS USING FULLY PROCESSED TEST TRANSISTORS IN HIGH-DENSITY PLASMA REACTORS FOR FAILURE ANALYSIS

The objective of this study was for it to serve as a guide for underst anding high density plasma induced damage during wafer fabrication and etchback for device debug, electron-beam, and failure analysis. A stu dy of electrical degradation of packaged and fully processed transisto rs that were functionally etched back was carried out. Two high densit y plasma technologies, electron cyclotron resonance (ECR) and inductiv ely coupled plasma (ICP), from various vendors, were evaluated. Transc onductance (got), threshold voltage (Vt), subthreshold slope, and gate leakage (Ig) were measured before and after the functional etch, Degr adation took place even without polysilicon being directly exposed to the plasma. It was found that there is a strong correlation between th e threshold voltage shift, and gate current shift, and they exhibit a bimodal relationship. The gate edge intensive transistor was most susc eptible to degradation. The design of the etchers seemed to be the key factor rather than the choice of technology (ECR or ICP) with regard to transistor degradation. Gate oxide breakdown due to the charging of metal lines, caused by nonuniform electrical charging of the surface, adequately explains the observed transistor parameter shifts. (C) 199 7 American Institute Vacuum Society.