A UNIFIED MODEL FOR THE SELF-LIMITING HOT-CARRIER DEGRADATION IN LDD N-MOSFET

A new insight into the self-limiting hot-carrier degradation in lightl y-doped drain (LDD) n-MOSFET's is presented, The proposed model is bas ed on the charge pumping (CP) measurement, By progressively lowering t he gate base level, the channel accumulation layer is caused to advanc e into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed, This forms the basis of a novel tech nique, that allows the contributions to the CP current, due to stress- induced interface states in the respective regions, to be effectively separated, Results show that interface state generation initiates in t he spacer oxide region and progresses rapidly into the overlap/channel region with stress time, The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/c hannel regions deduced from CP data, pro,ides an unambiguous experimen tal evidence that the degradation proceeds in a two-stage mechanism, i nvolving first a series resistance increase and saturation, followed b y a carrier mobility reduction, The saturation in series resistance in crease results directly from a reduced interface state generation rate in the spacer oxide, For a given density of defect precursors and con sidering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhib it an exponential stress time dependence, with a characteristic time c onstant determined by the applied voltages, This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular str ess drain voltage V-d, may be extracted from a single composite degrad ation characteristic, obtained by shifting characteristics for various stress V-d's, along the stress time axis, until the characteristics m erge into a single curve.