MATCHING ANALYSIS OF DEPOSITION DEFINED 50-NM MOSFETS

NMOS- and PMOS-transistors with geometries down to 50 nm are fabricate d by conventional optical lithography using a deposition-and etchback technique for masking the polysilicon layer, The significant process s teps, especially the specific gate definition process and the doping o f the source/drain-extensions, are explained, These transistors are th en characterized and proceedings to increase their performance are sug gested, The local and global matching of sub-100-nm transistors is ana lyzed by a large number of measurements and compared to typical litera ture values and simulations, The law of area (sigma V-T proportional t o 1/root W.L) is confirmed for device dimensions from W/L = 10 mu m/1 mu m down to W/L = 1 mu m/50 nm, Based on this law of area, considerat ions to reduce the threshold voltage scattering for sub-100-nm transis tors will be suggested.