MODELING OF GATE LINE DELAY IN VERY LARGE ACTIVE-MATRIX LIQUID-CRYSTAL DISPLAYS

With standard inverted-staggered amorphous silicon based TFT's, the si ze of active matrix liquid crystal displays is restricted by the RC ti me constant of the gate conductor. This RC delay can be reduced consid erably by connecting the gate line through via holes to a bus run on t he hack side of the substrate. We use the SPICE model to examine the r elationship between the RC delay and all important circuit parameters. The results show that with a low-resistance hack line and only a few via holes per line, the delay can be reduced by nearly a factor of ten .