EFFECT OF FLOATING-BODY CHARGE ON SOI MOSFET DESIGN

This work presents a a new method far assessing the effect of floating -body charge on a fully- and partially-depleted Silicon-on-Insulator ( SOI) MOSFET device design spare. Floating-body effects under transient conditions are incorporated into the device design parameters thresho ld voltage V-T and off-current I-OFF using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the wors t-case bounds of the device design parameters, from idle to switching- steady-state, is presented and applied to a CMOS inverter example. Usi ng this methodology, the worst-case shifts in V-T and I-OFF due to hys teretic floating-body charge are quantified for devices in L-eff = 0.2 - and 0.1-mu m design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how seducing the effective bulk carries lifetime widens the 0.1-mu m design space.